This invention relates to a bit-line sense amplifier. More particularly, this invention relates to a high-speed, differential-feedback, cascode-type sense amplifier for a memory system.
A conventional memory system is organized into columns of storage cells. Coupled to each storage cell in the column is a pair of bit-sense lines. When reading a storage cell, the logic state of the select cell determines the relative current difference of the bit-sense lines. One bit-sense line has a first current signal level, while the other bit-sense line has a second current signal level. A sense amplifier is connected to the pair of bit-sense lines for amplifying the current difference across the bit-sense lines to generate an output data signal representative of an appropriate logic state. For example, in a memory system having an ECL sense amplifier, the current difference across the bit-sense lines is amplified to generate output signals having specified ECL voltage levels. For a memory read of a cell storing a logic high, the corresponding current difference appearing across the bit-sense lines is amplified to generate output signals having an ECL logic high voltage level. Similarly, for a memory read of a cell storing a logic low, the corresponding current difference appearing across the bit-sense lines is amplified to generate an output signal having an ECL logic low voltage level.
Columns of memory have a very large capacitive load. To decrease the access time, the column capacitance and/or the parasitic voltage difference across the pair of bit-sense lines are reduced. Column capacitance is determined by the memory organization, topography and fabrication process. For large memories, the large column capacitances are unavoidable. Accordingly, to achieve a high speed sense amplifier it is desireable to provide minimal parasitic voltage difference across the bit-sense lines.
FIG. 1 shows a conventional sense amplifier 10, including resistors 12, 14 and differential amplifier 16. The bit sense line data signal d.sub.o and inverted data signal d.sub.-- b.sub.o are fed into the non-inverting and inverting terminals of the differential amplifier 16, respectively. Resistor 12 is coupled to the bit-sense line which carries the inverted data signal d.sub.--b.sub.o, while the resistor 14 is coupled to the bit-sense line which carries the data signal d.sub.o. The differential amplifier 16 amplifies the difference of the input signals to generate the sense amplifier output signal d.sub.out.
The resistors 12, 14 translate the currents of the respective bit-sense lines into voltage signals. Thus, the resistors 12, 14 determine the voltage difference between the two input signals d.sub.o and d.sub.-- b.sub.o. For larger resistances, the memory access time is slow. Accordingly, lower resistances are desired for achieving faster access times. However, if low resistances are used to achieve a small voltage difference, the circuitry for the differential amplifier 16 becomes more complex. For a desirably small voltage difference, the complexity of the differential amplifier circuitry 16 results in an undesirably slow amplifier 16. For the complex amplifier 16 to amplify the voltage difference to the needed voltage level, the switching time becomes undesirably slow. As a result, the fast access time anticipated at the small voltage difference is offset by the decrease in speed of amplifier 16. Thus, a typical voltage difference across the bit-sense lines for an ECL amplifier 10 is approximately 300 mV. This results in an access time of approximately 12 nano-seconds. Accordingly, a smaller voltage difference is desired.
FIG. 2 shows another conventional sense amplifier--a cascode sense amplifier 20. The amplifier 20 includes the resistors 12, 14 and the differential amplifier 16 of FIG. 1, and also adds a pair of transistors 22, 24. The differential amplifier 16 is cascoded to the outputs of the transistors 22, 24. The bit-sense line which carries the data signal d.sub.o is coupled to the emitter of transistor 24, while the bit-sense line which carries the inverted data line d.sub.-- b.sub.o is coupled to the emitter of transistor 22. The respective bases of transistors 22, 24 are tied to a reference voltage V.sub.ref. The reference voltage V.sub.ref biases the transistors 22, 24 enabling the respective data signals to flow to the differential amplifier 16 inputs. The transistors 22, 24 serve to amplify the data and inverted data signals d.sub.o and d.sub.-- b.sub.o, respectively. A typical parasitic voltage difference across the bit-sense lines for an ECL cascode sense amplifier 20 is approximately 50 mV, resulting in an access time of approximately 2 nano-seconds.
A problem with amplifier 20 is an undesirable sensitivity to common mode noise. Noise generated on the power supply lines or the bit-sense lines may cause the transistors 22, 24 to shut off completely, resulting in glitches in the sense amplifier output signal d.sub.out.
FIG. 3 shows yet another conventional sense amplifier 30, including a cross-coupled cascode clamp described in the publication "A 3.5 ns, 1 Watt, ECL Register File," by Horowitz et. al., 1990 IEEE International Solid-State Circuits Conference, presented Feb. 14, 1990. (IEEE publication no. 0193-6530/90/0000-0068). The amplifier 30 includes the differential amplifier 16 of FIG. 1, along with the cross-coupled cascode clamp 32 of Horowitz et. al. The clamp 32 includes resistors 12, 14 (comparable to those of FIGS. 1 and 2), resistors 34, 36, transistors 38, 40, 42, 44 and current sources 46, 48. The transistors 38, 40 perform similarly to the transistors 22, 24 of FIG. 2. The resistors 34, 36 and transistors 42, 44 are included for reducing the common mode noise problem of the amplifier 20 of FIG. 2. Resistors 34, 36 are coupled to a supply voltage. The transistors 42, 44 with resistors 34, 36 bias the base voltages of transistors 38, 40 so as to filter noise spikes. As a result, the bases of transistors 38, 40 are referenced to differential voltage levels which move so as to reduce the needed voltage difference across the bit-sense lines. A typical voltage difference across the bit-sense lines for the amplifier 30 is approximately 30 mV, resulting in an access time of approximately 1.2 nano-seconds.
Of the conventional sense amplifiers described, the sense amplifier 30 of FIG. 3 provides the lowest voltage difference and fastest access time, while reducing sensitivity to common mode noise. As the circuit for reducing the sensitivity to common mode noise limits the minimum voltage difference across the bit-sense lines (and thus limits the access time), there is a continuing need for reducing the voltage difference while maintaining a satisfactory common mode noise rejection level.